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Wanted to pass along that issues with "Gate Capacitance" as well as Inductive Reactance to affect Rise and Fall times - so what you may be seeing as "negative" in the FET may simply be issue around the "Expansion" effects not of the fields present, but their thermal effects distorting the Die and therefore it's layout.

That, along with Gate FET insulation  - onto the dimensioning and then onto the spacing of layers and junctions...then adding to this are the problems with "zenering" (the protection device) of the base layer onto the (integrated) inherited traits of their junctions - the "negative" you see is more of the "avalanche" effect from the zener in the base substrate. It stays active through out the time it's "activated" unto when the power is finally switched off.

• So you think Transistors are fun, at least they are physically junctioned together - MOSFET's are like a Peanut Butter Sandwich - Where's the Jelly when you need it?

To activate that Zener - its a lot like a thermal detonator - you "push to test"  <*click*> - then RELEASE to Detonate - Now what? You pull power before it self destructs - the inductive event on the output along with the capacitive surface the gate has, makes this a self-sustaining event until power is removed and the Zener can reset. You have to build in your own Self-protect feature in this matter - else the device will continue to stay latched and self-destruct.

Seem this event happens a lot in 13N10's not because of reverse breakdowns, the Gates are failing...The 13N10

"burn out" because of - I call it a distortion - a gate substrate "section" just plain opens up like a tear and the device is toast.

VMOS or TRENCH FET designs are suffering a similar fate...