If you want to use a 11.325 crystal in a 11.1125 radio, pretty sure you just lift pin 10. Vice versa going the other way. The washington and 142 with the 11.1125 crystal had pin 10 (P6) low while the 148 and grant with the 11.325 crystal had the pin floating (high, internal pull-up). Other than P6 (pin 10), I think the rest of the N code is the same regardless of crystal. It works in my MB8719 spreadsheet that way too.
What we need is a chart for whatever pin configurations you want for the crystal yours uses (regardless of whether it belongs there or not). What pin configurations do we want to try?
P0-P5 are controlled via channel dial, P6 is factory low (washington, 142) or high (148, grant) with pin not connected (internal pull up). There is a P7, but it is controlled internally by an inverted copy of P6 (more on this in a moment).
The simplest switch mod would be to have a high and low on P6 (basically ground it or not). A second switch would likely appear on P5. Since P5 is on the channel dial, having a switchable inverter here would be ideal, but some may just run that pin manual - isolating it from the channel dial (and screwing it up).
There is also the possibility for the MB8719 (not the RCI8719) to pull the voltage somewhere mid-rail on pin 10 (P6) using a resistor to ground. I have not tried it yet, but I have read that the threshold on the internal P7 inverter is higher than the input to P6 allowing both to be high at the same time given the proper voltage on P6. I think the RCI version removed that flaw. One of these days, I will lift pin 10 in my washington and see how many times my counter changes frequency with a pot to ground at pin 10, I just don't know the internal pull-up value so its a guess on the test pot range.
Anyone want to double-check this for me?

Edit: this chart shows one interesting thing, only the 11.325 crystal can get you to the triple nickel if the float trick doesn't work on your PLL. With the 11.1125 crystal, P6 and P7 must both be high to get the triple nickel, and that depends on the design flaw being present in the chip.