Looking into the amp. I've got a nice 0 to 4.5 V or so at TP4. I went back and compared the VCO output to the loop downmix signal for the loop mixer, both are hitting their respective gates at about .4 V, so that may acceptable since TR15 is doing it's job.
I decided to check another scenario. What if the new VCO is good and one of the dividers or the phase comparator is the problem now?
To test this, I tweaked the VCO to get as close to 19.1675 as I could (Channel 13, USB, clarifier centered in the alignment procedure). I checked to make sure the fixed divider looked good, and it's putting out a 10kHz square wave. I then checked the programmable divider and it's putting out a high signal with negative spikes at about 8 kHz. Yeah, that's a problem.
So now I get to do math and take readings to figure out if:
1. All of my oscillators are doing their thing at the correct frequencies.
2. All of my mixers are outputting the proper signals.
3. All of my programmable divider inputs are correct.
4. My programmable divider output is correct for the given inputs.
Until I get the programmable divider output at least close to the fixed divider the loop will never lock. Kind of important in a PLL circuit, last I checked.
I decided to check another scenario. What if the new VCO is good and one of the dividers or the phase comparator is the problem now?
To test this, I tweaked the VCO to get as close to 19.1675 as I could (Channel 13, USB, clarifier centered in the alignment procedure). I checked to make sure the fixed divider looked good, and it's putting out a 10kHz square wave. I then checked the programmable divider and it's putting out a high signal with negative spikes at about 8 kHz. Yeah, that's a problem.
So now I get to do math and take readings to figure out if:
1. All of my oscillators are doing their thing at the correct frequencies.
2. All of my mixers are outputting the proper signals.
3. All of my programmable divider inputs are correct.
4. My programmable divider output is correct for the given inputs.
Until I get the programmable divider output at least close to the fixed divider the loop will never lock. Kind of important in a PLL circuit, last I checked.
