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RocketBox HD500 w/9530 FETs

I disagree completely. FET's do not have the negative temperature coefficient like the bipolars. There is very little to match other than the part numbers. The Rds on does not vary much often less than 10%. Most of the time less than 5%. The input capacitance does not vary very much either. The Vgs varies some but with a spread of less than .3 volts it is hard to get fanatical about that.
Using a radio that has been SCREW drivered is more of a problem.
Messing with the harmonic filters for extra output is just plain stupid.


9948B79D-5B08-4AA7-B200-98CFD5B6A667.png
 
That's pretty drastic and it gets exponentially worse the more you have working in parallel.
The 98vhp is a prime example. That's where those matched Palomar transistors come in handy. Naturally a service manual isn't going to help you solve the issue.

Why does it have to be “Palomar”? Why couldn’t it be any other brand? Why am I not surprised you said that less than .3 was drastic?

drastic
adjective
dras·tic | \ ˈdra-stik \
Definition of drastic


1: acting rapidly or violently a drastic purgative
2: extreme in effect or action : SEVERE

I think the reasonable people will agree that drastic isn’t exactly the correct word to use there. Maybe if he said greater than .5 or 1.0 and higher, then drastic would’ve fit better.

To say it would have a drastic effect, based on that definition, would mean that radio wouldn’t last more than a few key ups. We all know that’s not true, think of the ones that come out of the box with mismatched gate voltages.

I think what would be more important than .3 or less would be little to no heatsink compound or excessive amounts of it. Heat is what kills mosfets faster than anything else.
 
Learned the hard way to take every new sleeve of FQP MOSFETs and check the Vgs. Gets jotted onto the rear of the part with a Sharpie.

Makes matching a pair, set of four or eight much faster when it's time to install them.

Just how much you can mismatch them without causing trouble is anybody's guess. Never really tried to find out.

73
 
Learned the hard way to take every new sleeve of FQP MOSFETs and check the Vgs. Gets jotted onto the rear of the part with a Sharpie.
73

I would not say it is not necessary at all. I have intentionally mismatched some FET transistors and the results were not catastrophic. The transistor that has the lowest RDSon will heat up and sort of match up to the other fet in the circuit.
In one amp I just matched the transistor in pairs and installed them in to an eight pill FET amp. The only problem I found was that one pair had a very slight symmetry difference less than .1 volt on the out put.
The combiner and the balancing resistors did not get hot.
 
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How important it is to match FETs is very dependant on the circuit surrounding them.
If you have a circuit like the amp in a Connex 4400-Turbo or a Galaxy 98VHP where you have 4 Mosfets all having their bias voltage set by a single adjustment POT, then matching of the VGS(th) _can_ be extremely important. How closely they need to be matched can be debated, but they definitely should be fairly close. I set all of my biasing based on measured drain current, just like you would with a real RF Mosfet. I couldn't care less what the gate voltage is because VGS(th) can vary quite a lot between batches of transistors, even from reputable sources. I know that 0.3V (300mV) doesn't sound like a lot, but yes, it _can_ be a drastic difference. Remember, devices like the IRF520, 13N10, ERF2030, and the ERF9530 are not RF amplifier Mosfets, they are switching Mosfets, and they are designed to have a narrow linear operating area to allow for a fast transition from fully off to fully on. 300mV could mean the difference between 2mA or 2A of quiescent current, both of which are bad in different ways when it comes to a linear amplifier.
Now, if you have a circuit that has a separate bias adjustment for each individual Mosfet, very close matching of VGS(th) is essentially a moot point, since you can set the quiescent current of each FET individually to the same amount. Ideally this is the best way to setup a Mosfet biasing network as far as I'm concerned.
As far as the RDS(on) variance is concerned, in a linear amplifier circuit, it doesn't matter much as the FETs should never be driven fully on into their resistive area in the first place. We're working in the linear region here. RDS(on) would matter more in something like a Class-E switching amplifier with power supply/direct polar modulation.
And finally, the temperature coefficients. It is true that, in general, the RDS(on) of a Mosfet has a PTC curve. Meaning as it heats up, the drain-source resistance increases, lowering current flow, and allowing self balancing between parallel FETs. I think this is more applicable in switching applications, but it might apply in linear region operation, I'm not sure. On the other hand, the VGS vs. IDS relationship is NTC and to a much greater effect. Meaning, for a static gate voltage, as the Mosfet heats up, it is going to draw more current, further heating up the device, and causing a runaway situation. This is why the biasing circuits for real RF Mosfets and high quality commercial amplifiers have temperature compensation, to prevent runaway.
So, yes, matching _can_ matter, but it is dependant upon the use case and the surrounding circuit design.
 
Well the circuit have capacitors that vary over 20%, Most resistors 10% and who know what on the inductors It does not seem any reason to get worked up over the variances on the fets. You do not bias the FET's for a quiescent current. They have an leakage current and the FET's are called "Enhanced Mode."
 
Well the circuit have capacitors that vary over 20%, Most resistors 10% and who know what on the inductors It does not seem any reason to get worked up over the variances on the fets. You do not bias the FET's for a quiescent current. They have an leakage current and the FET's are called "Enhanced Mode."

Yes, and those tolerances can sometimes matter also. The higher the power and higher the frequency, the more it can matter, depending on what part of the circuit we're talking. They do matter much less though, and good designs will have reasonable tolerance acceptance factored into their designs. Those tolerances aren't going to cause a massive difference in idle current through the FETs or cause them to be biased way off of where their load line should be set either, which was the point I was getting at.
And yes, you do bias FETs for a quiescent drain current, why wouldn't you? If you're just setting gate voltages, then you have no idea of where on the load line the devices are being biased due to variations in VGS(th). It could be almost anywhere. You could have 1 FET being driven into compression while another is barely turning on. That's an extreme example, but you get the point.
Bipolars have leakage current through the C-E junction just like FETs leak through the D-S junctions, that has zero at all to do with how you bias them. Depletion and enhancement mode just describes how the D-S channel operates. Depletion FETs require a negative gate voltage to cut-off channel current, enhancement mode FETs cut-off at 0 or positive voltage.
Having said that, every FET datasheet I've ever read, from J310 depletion JFETs and dual-gate Mosfets, clear up to >1KW LDMOS enhancement Mosfet devices, they all specify biasing conditions as IDQ, quiescent drain current. You need to know the no-signal drain current to be able to do the load line calculations for the designing stage. Once the circuit is designed, you can set the biasing by measuring the drain current and you'll be spot on, every time, regardless of any variation in VGS(th).
I'm self-taught, so I just go by the books that I've read. They all say to bias RF Power Mosfets by the drain current, and I've never had any issues as of yet. I don't see why it would be any different when using switching FETs in RF applications. The same rules apply. I'm always up for learning something new though.
 
Yes, and those tolerances can sometimes matter also. The higher the power and higher the frequency, the more it can matter, depending on what part of the circuit we're talking. They do matter much less though, and good designs will have reasonable tolerance acceptance factored into their designs. Those tolerances aren't going to cause a massive difference in idle current through the FETs or cause them to be biased way off of where their load line should be set either, which was the point I was getting at.
And yes, you do bias FETs for a quiescent drain current, why wouldn't you? If you're just setting gate voltages, then you have no idea of where on the load line the devices are being biased due to variations in VGS(th). It could be almost anywhere. You could have 1 FET being driven into compression while another is barely turning on. That's an extreme example, but you get the point.
Bipolars have leakage current through the C-E junction just like FETs leak through the D-S junctions, that has zero at all to do with how you bias them. Depletion and enhancement mode just describes how the D-S channel operates. Depletion FETs require a negative gate voltage to cut-off channel current, enhancement mode FETs cut-off at 0 or positive voltage.
Having said that, every FET datasheet I've ever read, from J310 depletion JFETs and dual-gate Mosfets, clear up to >1KW LDMOS enhancement Mosfet devices, they all specify biasing conditions as IDQ, quiescent drain current. You need to know the no-signal drain current to be able to do the load line calculations for the designing stage. Once the circuit is designed, you can set the biasing by measuring the drain current and you'll be spot on, every time, regardless of any variation in VGS(th).
I'm self-taught, so I just go by the books that I've read. They all say to bias RF Power Mosfets by the drain current, and I've never had any issues as of yet. I don't see why it would be any different when using switching FETs in RF applications. The same rules apply. I'm always up for learning something new though.

You are imposing bipolar characteristics on fet's and that''s why you get confused. I have never seen any body measure the source current to balance and bias the amp because it is not necessary. As long as you gate bias is set and the FETS are of the same VGSon you are good to go. If the situation occurs where you have a fet just barely starting to conduct and another one is full on your drive circuits are screwed up not the fets. Or you have mixed fet's of a different part number and the VGSon is completely wrong. Other tha that I have to call B.S.on the rest of it.
 

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